【疑问解答】数码管实验全编译报时钟警告

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Warning (12010): Port "probe" on the entity instantiation of "altsource_probe_component" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be driven by GND.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: HEX8:HEX8|clk_1K was determined to be a clock but was found without an associated clock assignment.


解决方案：
新建一个SDC格式的文件，将下述内容复制粘贴到文件中，然后将该文件保存为HEX_top.sdc，然后添加到工程中，再编译就可以了。

1. 
   
2. #**************************************************************
   
3. # Time Information
   
4. #**************************************************************
   
5. 
   
6. set_time_format -unit ns -decimal_places 3
   
7. 
   
8. 
   
9. 
   
10. #**************************************************************
    
11. # Create Clock
    
12. #**************************************************************
    
13. 
    
14. create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
    
15. create_clock -name {Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {Clk}]
    
16. 
    
17. 
    
18. #**************************************************************
    
19. # Create Generated Clock
    
20. #**************************************************************
    
21. 
    
22. create_generated_clock -name {clk1k} -source [get_ports {Clk}] -divide_by 50000 -master_clock {Clk} [get_registers {HEX8:HEX8|clk_1K}]
    
23. 
    
24. 
    
25. #**************************************************************
    
26. # Set Clock Latency
    
27. #**************************************************************
    
28. 
    
29. 
    
30. 
    
31. #**************************************************************
    
32. # Set Clock Uncertainty
    
33. #**************************************************************
    
34. derive_clock_uncertainty
    
35. 
    
36. 
    
37. #**************************************************************
    
38. # Set Input Delay
    
39. #**************************************************************
    
40. 
    
41. 
    
42. 
    
43. #**************************************************************
    
44. # Set Output Delay
    
45. #**************************************************************
    
46. 
    
47. 
    
48. 
    
49. #**************************************************************
    
50. # Set Clock Groups
    
51. #**************************************************************
    
52. 
    
53. set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
    
54. set_clock_groups -asynchronous -group [get_clocks {Clk clk1k}]
    
55. 
    

复制代码

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