本帖最后由 000 于 2019-2-14 02:09 编辑
- module mixed_width_ram_v
- #(
- parameter Write_Width = 16, //双字节存储
- parameter Depth = 64,
- parameter Read_Width = 8 //单字节读出
- )
- (
- input write_ena,
- input clk,
- input [log2(Depth) - 1 : 0] write_addr,
- input [Write_Width - 1 : 0] write_data,
- input [log2(Depth) + log2(Ratio) - 1 : 0] read_addr,
- output reg [Read_Width -1 : 0] q
- );
- localparam Ratio = Write_Width / Read_Width;
- function integer log2 (input integer bit_depth);
- begin
- bit_depth = bit_depth - 1;
- for(log2 = 0; bit_depth > 0; log2 = log2 + 1)
- bit_depth = bit_depth >> 1;
- end
- endfunction
- reg [Read_Width -1 : 0] ram[Depth - 1 : 0][Ratio - 1 : 0];
- always@(posedge clk)
- begin
- q <= ram[read_addr / Ratio][read_addr % Ratio];
- end
-
- //////////////////////////////////////////////////////////////////////////////////////////
- ///////////////////////////////////以下四种代码////////////////////////////////////////////
- ////////////////////////////////////////////一: generate综合成逻辑门,资源爆炸
- // genvar j;
- // generate
- // for (j = 0; j < Ratio; j = j + 1)
- // begin:genname
- // always@(posedge clk)
- // begin
- // if(write_ena)
- // begin
- // ram[write_addr][j] <= write_data[Read_Width*(j+1)-1 : Read_Width*j];
- // end
- // end
- // end
- // endgenerate
- ////////////////////////////////////////////二:generate等效语句,弹窗式错误
- // always@(posedge clk)
- // begin
- // if(write_ena)
- // begin
- // ram[write_addr][1] <= write_data[Read_Width*(1+1)-1 : Read_Width*1];
- // end
- // end
- // always@(posedge clk)
- // begin
- // if(write_ena)
- // begin
- // ram[write_addr][0] <= write_data[Read_Width*(0+1)-1 : Read_Width*0];
- // end
- // end
- ////////////////////////////////////////////三:效果最好,综合成专用存储单元
- // always@(posedge clk)
- // begin
- // if(write_ena)
- // begin
- // ram[write_addr][1] <= write_data[Read_Width*(1+1)-1 : Read_Width*1];
- //
- // ram[write_addr][0] <= write_data[Read_Width*(0+1)-1 : Read_Width*0];
- // end
- // end
- ////////////////////////////////////////////四: for循环参数化模块出错
- // integer j;
- // always@(posedge clk)
- // begin
- // if(write_ena)
- // begin
- // for (j = 0; j < Ratio; j = j + 1)
- // begin
- // ram[write_addr][j] <= write_data[Read_Width*(j+1)-1 : Read_Width*j]; //129行这里出错
- // end
- // end
- // end
-
-
-
-
- endmodule
复制代码 参数化模块时遇到各种疑难杂症
////////////////////////////////////////////一: generate综合成逻辑门,资源爆炸
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 14 00:24:31 2019 ;
; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
; Revision Name ; study ;
; Top-level Entity Name ; mixed_width_ram_v ;
; Family ; Cyclone IV E ;
; Device ; EP4CE10F17C8 ;
; Timing Models ; Final ;
; Total logic elements ; 1,274 / 10,320 ( 12 % ) ;
; Total combinational functions ; 752 / 10,320 ( 7 % ) ;
; Dedicated logic registers ; 1,032 / 10,320 ( 10 % ) ;
; Total registers ; 1032 ;
; Total pins ; 39 / 180 ( 22 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 423,936 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
////////////////////////////////////////////二:generate等效语句,弹窗式错误
*** Fatal Error: Access Violation at 0X000007FEDF882CA0 Module: quartus_map.exe Lock in use: 53 Stack Trace: 0x12c9f: CDB_SGATE_OPERATOR::mls_sweep + 0x41f 0xad8f: OPT_RAM_AI::OPT_RAM_AI + 0x7aff 0x9a0b: OPT_RAM_AI::OPT_RAM_AI + 0x677b 0x8e46: OPT_RAM_AI::OPT_RAM_AI + 0x5bb6 0xb5d0: RTL_ROOT::post_extraction_processing + 0x6e0 0x14ec4: RTL_ROOT::post_extraction_processing + 0x9fd4 0x1490e: RTL_ROOT::post_extraction_processing + 0x9a1e 0x1312c: RTL_ROOT::post_extraction_processing + 0x823c 0x5459c: RTL_ROOT::process_sgate_netlist + 0x1dc 0x13e001: sgn_clear_check_ip_functor + 0xb3e01 0x1400e8: sgn_clear_check_ip_functor + 0xb5ee8 0xa41d6: sgn_clear_check_ip_functor + 0x19fd6 0xa6a44: sgn_clear_check_ip_functor + 0x1c844 0xa73ca: sgn_clear_check_ip_functor + 0x1d1ca 0x10e17: sgn_qic_full + 0x257
0x11fad: qexe_get_command_line + 0x1b7d 0x14e0e: qexe_process_cmdline_arguments + 0x59e 0x14f21: qexe_standard_main + 0xa1
0x4ae8: msg_exe_fini + 0x58 0x522c: msg_exe_fini + 0x79c 0x1524: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194 0x5e0f: msg_exe_main + 0x8f
0x159cc: BaseThreadInitThunk + 0xc 0x2a560: RtlUserThreadStart + 0x20
End-trace
Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
////////////////////////////////////////////三:效果最好,综合成专用存储单元
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 14 00:30:31 2019 ;
; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
; Revision Name ; study ;
; Top-level Entity Name ; mixed_width_ram_v ;
; Family ; Cyclone IV E ;
; Device ; EP4CE10F17C8 ;
; Timing Models ; Final ;
; Total logic elements ; 0 / 10,320 ( 0 % ) ;
; Total combinational functions ; 0 / 10,320 ( 0 % ) ;
; Dedicated logic registers ; 0 / 10,320 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 39 / 180 ( 22 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,024 / 423,936 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
////////////////////////////////////////////四: for循环参数化模块出错
Error (10734): Verilog HDL error at mixed_width_ram_v.v(129): j is not a constant
虚心求教如何才能正确参数化此模块
|