TA的每日心情 | 萌哒 2020-7-2 11:17 |
---|
新手入门
- 积分
- 15
|
//顶层模块,ADC模块在后面
module top_adc1208(
input wire clk,
input wire rst_n,
input wire ADC_DOUT,
output wire ADC_CLK,
output wire ADC_CS_n,
output wire ADC_DIN,
output reg [3:0] led
);
wire [2:0] channel;
wire [11:0] data;
wire ADC_Ding;
adc128s022 adc128s022_inst(
.clk (clk),
.rst_n (rst_n),
.channel (channel),//ADC通道选择
.En_Conv (ADC_Ding),//单周期使能信号
.ADC_DOUT (ADC_DOUT),//ADC转换结果输出给FPGA
.ADC_CLK (ADC_CLK),//ADC时钟信号,由FPGA给ADC
.ADC_DIN (ADC_DIN),//ADC通道选择,由FPGA给ADC
.ADC_CS_n (ADC_CS_n),//ADC使能信号
.data (data),//FPGA将接受的ADC转换数据输出
.ADC_Ding (ADC_Ding)//转换完成信号
);
//ISSP IP核
ts ts_inst (
.probe ( {data,channel} ),
.source ( channel )
);
endmodule
//ADC模块
module adc128s022(
input wire clk,
input wire rst_n,
input wire [2:0] channel,//ADC通道选择,外部给与,再由FPGA给ADC
input wire En_Conv,//单周期使能信号
input wire ADC_DOUT,//ADC转换结果输出给FPGA
output reg ADC_CLK,//ADC时钟信号,由FPGA给ADC
output reg ADC_DIN,//ADC通道选择,由FPGA给ADC
output reg ADC_CS_n,//ADC使能信号
output reg [11:0] data,//FPGA将接受的ADC转换数据并行输出
output reg ADC_Ding//转换完成信号(数据已经并行输出)
);
parameter DIV_MAX = 4'd12;//分频计数器最大值(fclk/DIV_MAX*2)
reg [2:0] r_channel;//通道选择寄存
reg [11:0] r_data;//寄存转换结果
reg en;//使能信号
reg [3:0] div_cnt;//分频计数器
reg flag;//计数标志
reg [5:0] cnt;//序列计数器
//在每个使能转换的时候,寄存Channel的值,防止在转换过程中该值发生变化
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
r_channel <= 3'd0;
else if(En_Conv)
r_channel <= channel;
else
r_channel <= r_channel;
end
//单脉冲使能信号
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
en <= 1'b0;
else if(En_Conv)
en <= 1'b1;
else if(ADC_Ding)
en <= 1'b0;
else
en <= en;
end
//分频计数器
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
div_cnt <= 4'd0;
else if(en)begin
if(div_cnt == DIV_MAX)
div_cnt <= 4'd0;
else
div_cnt <= div_cnt + 1'b1;
end
else
div_cnt <= 4'd0;
end
//计数标志
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
flag <= 1'b0;
else if(en && (div_cnt == DIV_MAX))
flag <= 1'b1;
else
flag <= 1'b0;
end
//序列计数器
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 6'd0;
else if(en && flag)begin
if(cnt == 6'd33)
cnt <= 6'd0;
else
cnt <= cnt + 1'b1;
end
else
cnt <= cnt;
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)begin
ADC_CLK <= 1'b1;
ADC_DIN <= 1'b1;
ADC_CS_n <= 1'b1;
r_data <= 12'd0;
end
else if(en)begin
if(flag)begin
case(cnt)
6'd0 : ADC_CS_n <= 1'b0;
6'd1 : begin ADC_CLK <= 1'b0; ADC_DIN <= 1'b0;end
6'd2 : ADC_CLK <= 1'b1;
6'd3 : ADC_CLK <= 1'b0;
6'd4 : ADC_CLK <= 1'b1;
6'd5 : begin ADC_CLK <= 1'b0; ADC_DIN <= r_channel[2];end
6'd6 : ADC_CLK <= 1'b1;
6'd7 : begin ADC_CLK <= 1'b0; ADC_DIN <= r_channel[1];end
6'd8 : ADC_CLK <= 1'b1;
6'd9 : begin ADC_CLK <= 1'b0; ADC_DIN <= r_channel[0];end
//每个上升沿,寄存ADC串行数据输出线上的转换结果
6'd10,6'd12,6'd14,6'd16,6'd18,6'd20,6'd22,6'd24,6'd26,6'd28,6'd30,6'd32:
begin ADC_CLK <= 1'b1; r_data <= {r_data[10:0], ADC_DOUT}; end //循环移位寄存DOUT上的12个数据
6'd11,6'd13,6'd15,6'd17,6'd19,6'd21,6'd23,6'd25,6'd27,6'd29,6'd31:
begin ADC_CLK <= 1'b0; end
default : ;
endcase
end
else ;
end
else
ADC_CS_n <= 1'b1;
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)begin
data <= 12'd0;
ADC_Ding <= 1'b0;
end
else if(en && flag && (cnt == 6'd33))begin
data <= r_data;
ADC_Ding <= 1'b1;
end
else begin
data <= data;
ADC_Ding <= 1'b0;
end
end
endmodule
|
|