Warning (332009): The launch and latch times for the relationship between source clock: PLL|altpll_component|auto_generated|pll1|clk[3] and destination clock: PLL|altpll_component|auto_generated|pll1|clk[0] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "Sd_CS_N" is stuck at GND
Warning (13410): Pin "Sd_Dqm[0]" is stuck at GND
Warning (13410): Pin "Sd_Dqm[1]" is stuck at GND