Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\gao_project\56_ov5640x2_udp_rgmii\ov5640x2_udp_rgmii\src\dc_fifo\temp\FIFO\fifo_define.v
H:\01_gaoyun\gao_project\56_ov5640x2_udp_rgmii\ov5640x2_udp_rgmii\src\dc_fifo\temp\FIFO\fifo_parameter.v
H:\0_gaoyun_p\1.9.9Beta_5\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\FIFO\data\edc.v
H:\0_gaoyun_p\1.9.9Beta_5\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\FIFO\data\fifo.v
H:\0_gaoyun_p\1.9.9Beta_5\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-5
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Mon Oct 16 13:58:27 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module dc_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 38.004MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.004MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.004MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.004MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 38.004MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.004MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.004MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.004MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.004MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 38.004MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.004MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.004MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.511s, Peak memory usage = 43.641MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 43.641MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 43.641MB
Total Time and Memory Usage CPU time = 0h 0m 0.982s, Elapsed time = 0h 0m 1s, Peak memory usage = 43.641MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 51
I/O Buf 51
    IBUF 13
    OBUF 38
Register 144
    DFFPE 5
    DFFCE 139
LUT 125
    LUT2 29
    LUT3 33
    LUT4 63
ALU 42
    ALU 42
INV 3
    INV 3
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 170(128 LUT, 42 ALU) / 23040 <1%
Register 144 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 144 / 23685 <1%
BSRAM 4 / 56 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I
fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n4_s2/O
fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n9_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.0(MHz) 173.1(MHz) 9 TOP
2 WrClk 100.0(MHz) 210.8(MHz) 8 TOP
3 fifo_inst/n4_6 100.0(MHz) 1577.9(MHz) 1 TOP
4 fifo_inst/n9_6 100.0(MHz) 1577.9(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.222
Data Arrival Time 6.561
Data Required Time 10.783
From fifo_inst/Empty_s0
To fifo_inst/Equal.mem_Equal.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 75 RdClk_ibuf/O
0.870 0.188 tNET RR 1 fifo_inst/Empty_s0/CLK
1.253 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.440 0.188 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.966 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.154 0.188 tNET RR 1 fifo_inst/rbin_num_next_5_s7/I1
2.670 0.516 tINS RR 9 fifo_inst/rbin_num_next_5_s7/F
2.858 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_6_s1/I1
3.374 0.516 tINS RR 5 fifo_inst/Equal.rgraynext_6_s1/F
3.561 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s2/I1
4.078 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s2/F
4.265 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s0/I1
4.781 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s0/F
4.969 0.188 tNET RR 2 fifo_inst/n124_s0/I0
5.525 0.556 tINS RF 1 fifo_inst/n124_s0/COUT
5.525 0.000 tNET FF 2 fifo_inst/n125_s0/CIN
5.575 0.050 tINS FR 1 fifo_inst/n125_s0/COUT
5.575 0.000 tNET RR 2 fifo_inst/n126_s0/CIN
5.625 0.050 tINS RR 1 fifo_inst/n126_s0/COUT
5.625 0.000 tNET RR 2 fifo_inst/n127_s0/CIN
5.675 0.050 tINS RR 1 fifo_inst/n127_s0/COUT
5.675 0.000 tNET RR 2 fifo_inst/n128_s0/CIN
5.725 0.050 tINS RR 2 fifo_inst/n128_s0/COUT
5.913 0.188 tNET RR 1 fifo_inst/n38_s1/I2
6.374 0.461 tINS RR 4 fifo_inst/n38_s1/F
6.561 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 75 RdClk_ibuf/O
10.870 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB
10.783 -0.087 tSu 1 fifo_inst/Equal.mem_Equal.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 3.809, 66.923%; route: 1.500, 26.356%; tC2Q: 0.382, 6.721%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 2

Path Summary:
Slack 4.222
Data Arrival Time 6.561
Data Required Time 10.783
From fifo_inst/Empty_s0
To fifo_inst/Equal.mem_Equal.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 75 RdClk_ibuf/O
0.870 0.188 tNET RR 1 fifo_inst/Empty_s0/CLK
1.253 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.440 0.188 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.966 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.154 0.188 tNET RR 1 fifo_inst/rbin_num_next_5_s7/I1
2.670 0.516 tINS RR 9 fifo_inst/rbin_num_next_5_s7/F
2.858 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_6_s1/I1
3.374 0.516 tINS RR 5 fifo_inst/Equal.rgraynext_6_s1/F
3.561 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s2/I1
4.078 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s2/F
4.265 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s0/I1
4.781 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s0/F
4.969 0.188 tNET RR 2 fifo_inst/n124_s0/I0
5.525 0.556 tINS RF 1 fifo_inst/n124_s0/COUT
5.525 0.000 tNET FF 2 fifo_inst/n125_s0/CIN
5.575 0.050 tINS FR 1 fifo_inst/n125_s0/COUT
5.575 0.000 tNET RR 2 fifo_inst/n126_s0/CIN
5.625 0.050 tINS RR 1 fifo_inst/n126_s0/COUT
5.625 0.000 tNET RR 2 fifo_inst/n127_s0/CIN
5.675 0.050 tINS RR 1 fifo_inst/n127_s0/COUT
5.675 0.000 tNET RR 2 fifo_inst/n128_s0/CIN
5.725 0.050 tINS RR 2 fifo_inst/n128_s0/COUT
5.913 0.188 tNET RR 1 fifo_inst/n38_s1/I2
6.374 0.461 tINS RR 4 fifo_inst/n38_s1/F
6.561 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 75 RdClk_ibuf/O
10.870 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB
10.783 -0.087 tSu 1 fifo_inst/Equal.mem_Equal.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 3.809, 66.923%; route: 1.500, 26.356%; tC2Q: 0.382, 6.721%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 3

Path Summary:
Slack 4.222
Data Arrival Time 6.561
Data Required Time 10.783
From fifo_inst/Empty_s0
To fifo_inst/Equal.mem_Equal.mem_0_1_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 75 RdClk_ibuf/O
0.870 0.188 tNET RR 1 fifo_inst/Empty_s0/CLK
1.253 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.440 0.188 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.966 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.154 0.188 tNET RR 1 fifo_inst/rbin_num_next_5_s7/I1
2.670 0.516 tINS RR 9 fifo_inst/rbin_num_next_5_s7/F
2.858 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_6_s1/I1
3.374 0.516 tINS RR 5 fifo_inst/Equal.rgraynext_6_s1/F
3.561 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s2/I1
4.078 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s2/F
4.265 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s0/I1
4.781 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s0/F
4.969 0.188 tNET RR 2 fifo_inst/n124_s0/I0
5.525 0.556 tINS RF 1 fifo_inst/n124_s0/COUT
5.525 0.000 tNET FF 2 fifo_inst/n125_s0/CIN
5.575 0.050 tINS FR 1 fifo_inst/n125_s0/COUT
5.575 0.000 tNET RR 2 fifo_inst/n126_s0/CIN
5.625 0.050 tINS RR 1 fifo_inst/n126_s0/COUT
5.625 0.000 tNET RR 2 fifo_inst/n127_s0/CIN
5.675 0.050 tINS RR 1 fifo_inst/n127_s0/COUT
5.675 0.000 tNET RR 2 fifo_inst/n128_s0/CIN
5.725 0.050 tINS RR 2 fifo_inst/n128_s0/COUT
5.913 0.188 tNET RR 1 fifo_inst/n38_s1/I2
6.374 0.461 tINS RR 4 fifo_inst/n38_s1/F
6.561 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_1_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 75 RdClk_ibuf/O
10.870 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB
10.783 -0.087 tSu 1 fifo_inst/Equal.mem_Equal.mem_0_1_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 3.809, 66.923%; route: 1.500, 26.356%; tC2Q: 0.382, 6.721%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 4

Path Summary:
Slack 4.222
Data Arrival Time 6.561
Data Required Time 10.783
From fifo_inst/Empty_s0
To fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 75 RdClk_ibuf/O
0.870 0.188 tNET RR 1 fifo_inst/Empty_s0/CLK
1.253 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.440 0.188 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.966 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.154 0.188 tNET RR 1 fifo_inst/rbin_num_next_5_s7/I1
2.670 0.516 tINS RR 9 fifo_inst/rbin_num_next_5_s7/F
2.858 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_6_s1/I1
3.374 0.516 tINS RR 5 fifo_inst/Equal.rgraynext_6_s1/F
3.561 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s2/I1
4.078 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s2/F
4.265 0.188 tNET RR 1 fifo_inst/Equal.rgraynext_9_s0/I1
4.781 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_9_s0/F
4.969 0.188 tNET RR 2 fifo_inst/n124_s0/I0
5.525 0.556 tINS RF 1 fifo_inst/n124_s0/COUT
5.525 0.000 tNET FF 2 fifo_inst/n125_s0/CIN
5.575 0.050 tINS FR 1 fifo_inst/n125_s0/COUT
5.575 0.000 tNET RR 2 fifo_inst/n126_s0/CIN
5.625 0.050 tINS RR 1 fifo_inst/n126_s0/COUT
5.625 0.000 tNET RR 2 fifo_inst/n127_s0/CIN
5.675 0.050 tINS RR 1 fifo_inst/n127_s0/COUT
5.675 0.000 tNET RR 2 fifo_inst/n128_s0/CIN
5.725 0.050 tINS RR 2 fifo_inst/n128_s0/COUT
5.913 0.188 tNET RR 1 fifo_inst/n38_s1/I2
6.374 0.461 tINS RR 4 fifo_inst/n38_s1/F
6.561 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 75 RdClk_ibuf/O
10.870 0.188 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB
10.783 -0.087 tSu 1 fifo_inst/Equal.mem_Equal.mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 3.809, 66.923%; route: 1.500, 26.356%; tC2Q: 0.382, 6.721%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 5

Path Summary:
Slack 5.256
Data Arrival Time 5.550
Data Required Time 10.806
From fifo_inst/Equal.wq2_rptr_10_s0
To fifo_inst/Wnum_13_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.683 0.683 tINS RR 75 WrClk_ibuf/O
0.870 0.188 tNET RR 1 fifo_inst/Equal.wq2_rptr_10_s0/CLK
1.253 0.382 tC2Q RR 2 fifo_inst/Equal.wq2_rptr_10_s0/Q
1.440 0.188 tNET RR 1 fifo_inst/Equal.rcount_w_10_s0/I0
1.966 0.526 tINS RR 4 fifo_inst/Equal.rcount_w_10_s0/F
2.154 0.188 tNET RR 1 fifo_inst/Equal.rcount_w_7_s0/I3
2.416 0.262 tINS RR 6 fifo_inst/Equal.rcount_w_7_s0/F
2.604 0.188 tNET RR 1 fifo_inst/Equal.rcount_w_2_s2/I1
3.120 0.516 tINS RR 2 fifo_inst/Equal.rcount_w_2_s2/F
3.307 0.188 tNET RR 1 fifo_inst/Equal.rcount_w_0_s0/I2
3.769 0.461 tINS RR 1 fifo_inst/Equal.rcount_w_0_s0/F
3.956 0.188 tNET RR 2 fifo_inst/wcnt_sub_0_s/I1
4.519 0.563 tINS RF 1 fifo_inst/wcnt_sub_0_s/COUT
4.519 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
4.569 0.050 tINS FR 1 fifo_inst/wcnt_sub_1_s/COUT
4.569 0.000 tNET RR 2 fifo_inst/wcnt_sub_2_s/CIN
4.619 0.050 tINS RR 1 fifo_inst/wcnt_sub_2_s/COUT
4.619 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
4.669 0.050 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
4.669 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
4.719 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
4.719 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
4.769 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
4.769 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
4.819 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
4.819 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
4.869 0.050 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
4.869 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
4.919 0.050 tINS RR 1 fifo_inst/wcnt_sub_8_s/COUT
4.919 0.000 tNET RR 2 fifo_inst/wcnt_sub_9_s/CIN
4.969 0.050 tINS RR 1 fifo_inst/wcnt_sub_9_s/COUT
4.969 0.000 tNET RR 2 fifo_inst/wcnt_sub_10_s/CIN
5.019 0.050 tINS RR 1 fifo_inst/wcnt_sub_10_s/COUT
5.019 0.000 tNET RR 2 fifo_inst/wcnt_sub_11_s/CIN
5.069 0.050 tINS RR 1 fifo_inst/wcnt_sub_11_s/COUT
5.069 0.000 tNET RR 2 fifo_inst/wcnt_sub_12_s/CIN
5.119 0.050 tINS RR 1 fifo_inst/wcnt_sub_12_s/COUT
5.119 0.000 tNET RR 2 fifo_inst/wcnt_sub_13_s/CIN
5.363 0.244 tINS RR 1 fifo_inst/wcnt_sub_13_s/SUM
5.550 0.188 tNET RR 1 fifo_inst/Wnum_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.682 0.683 tINS RR 75 WrClk_ibuf/O
10.870 0.188 tNET RR 1 fifo_inst/Wnum_13_s0/CLK
10.806 -0.064 tSu 1 fifo_inst/Wnum_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 3.172, 67.789%; route: 1.125, 24.038%; tC2Q: 0.382, 8.173%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%