Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\FX2_CDC_Loopback.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\SPI_Slave.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\fifo_1024x8.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\gowin_pll\gowin_pll.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\gowin_pll\gowin_pll_mod.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\hc595_driver.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\hex8.v
C:\Users\24165\Desktop\138k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\pll_init.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Fri Jul 25 11:53:27 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module FX2_CDC_Loopback
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 1504.895MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 1504.895MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 1504.895MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 1504.895MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 1504.895MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 1504.895MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 1504.895MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 1504.895MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 1504.895MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 1504.895MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 1504.895MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1504.895MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 1504.895MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 1504.895MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1504.895MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 29
I/O Buf 27
    IBUF 8
    OBUF 11
    IOBUF 8
Register 722
    DFFRE 457
    DFFPE 8
    DFFCE 257
LUT 721
    LUT2 75
    LUT3 396
    LUT4 250
ALU 52
    ALU 52
INV 6
    INV 6
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 779(727 LUT, 52 ALU) / 138240 <1%
Register 722 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 722 / 139095 <1%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 fx2_ifclk Base 10.000 100.000 0.000 5.000 fx2_ifclk_ibuf/I
2 SPI_SCLK Base 10.000 100.000 0.000 5.000 SPI_SCLK_ibuf/I
3 hex8/clk_1K Base 10.000 100.000 0.000 5.000 hex8/clk_1K_s2/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 fx2_ifclk 100.000(MHz) 133.601(MHz) 8 TOP
2 SPI_SCLK 100.000(MHz) 266.134(MHz) 4 TOP
3 hex8/clk_1K 100.000(MHz) 351.958(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.160
Data Arrival Time 4.181
Data Required Time 5.341
From SPI_Slave/Send_Data_R_2_s0
To SPI_Slave/MISO_s0
Launch Clk fx2_ifclk[F]
Latch Clk SPI_SCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fx2_ifclk
0.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
0.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
0.413 0.413 tNET RR 1 SPI_Slave/Send_Data_R_2_s0/CLK
0.795 0.382 tC2Q RR 1 SPI_Slave/Send_Data_R_2_s0/Q
1.207 0.413 tNET RR 1 SPI_Slave/n171_s20/I0
1.786 0.579 tINS RR 1 SPI_Slave/n171_s20/F
2.199 0.413 tNET RR 1 SPI_Slave/n171_s17/I0
2.778 0.579 tINS RR 1 SPI_Slave/n171_s17/F
3.190 0.413 tNET RR 1 SPI_Slave/n171_s21/I0
3.769 0.579 tINS RR 1 SPI_Slave/n171_s21/F
4.181 0.413 tNET RR 1 SPI_Slave/MISO_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 SPI_SCLK
5.000 0.000 tCL FF 1 SPI_SCLK_ibuf/I
5.000 0.000 tINS FF 34 SPI_SCLK_ibuf/O
5.385 0.385 tNET FF 1 SPI_Slave/MISO_s0/CLK
5.350 -0.035 tUnc SPI_Slave/MISO_s0
5.341 -0.009 tSu 1 SPI_Slave/MISO_s0
Path Statistics:
Clock Skew: -0.028
Setup Relationship: 5.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.736, 46.070%; route: 1.650, 43.781%; tC2Q: 0.382, 10.149%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 2.515
Data Arrival Time 7.834
Data Required Time 10.349
From delay_cnt_10_s0
To delay_cnt_0_s0
Launch Clk fx2_ifclk[R]
Latch Clk fx2_ifclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fx2_ifclk
0.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
0.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
0.413 0.413 tNET RR 1 delay_cnt_10_s0/CLK
0.795 0.382 tC2Q RR 5 delay_cnt_10_s0/Q
1.207 0.413 tNET RR 1 n170_s5/I0
1.786 0.579 tINS RR 1 n170_s5/F
2.199 0.413 tNET RR 1 n170_s1/I0
2.778 0.579 tINS RR 4 n170_s1/F
3.190 0.413 tNET RR 1 n164_s2/I0
3.769 0.579 tINS RR 2 n164_s2/F
4.181 0.413 tNET RR 1 n164_s0/I0
4.760 0.579 tINS RR 2 n164_s0/F
5.173 0.413 tNET RR 1 delay_en_s6/I1
5.740 0.567 tINS RR 1 delay_en_s6/F
6.153 0.413 tNET RR 1 delay_en_s5/I3
6.441 0.289 tINS RR 32 delay_en_s5/F
6.854 0.413 tNET RR 1 n129_s2/I1
7.421 0.567 tINS RR 1 n129_s2/F
7.834 0.413 tNET RR 1 delay_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 fx2_ifclk
10.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
10.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
10.413 0.413 tNET RR 1 delay_cnt_0_s0/CLK
10.349 -0.064 tSu 1 delay_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.739, 50.379%; route: 3.300, 44.467%; tC2Q: 0.382, 5.154%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 2.535
Data Arrival Time 7.779
Data Required Time 10.314
From SM_State_4_s4
To SM_State_3_s0
Launch Clk SPI_SCLK[R]
Latch Clk fx2_ifclk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 SPI_SCLK
5.000 0.000 tCL FF 1 SPI_SCLK_ibuf/I
5.000 0.000 tINS FF 34 SPI_SCLK_ibuf/O
5.385 0.385 tNET FF 1 SM_State_4_s4/I0
5.964 0.579 tINS FR 3 SM_State_4_s4/F
6.376 0.413 tNET RR 1 n1618_s8/I3
6.665 0.289 tINS RR 1 n1618_s8/F
7.078 0.413 tNET RR 1 n1618_s6/I3
7.366 0.289 tINS RR 1 n1618_s6/F
7.779 0.413 tNET RR 1 SM_State_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 fx2_ifclk
10.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
10.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
10.413 0.413 tNET RR 1 SM_State_3_s0/CLK
10.378 -0.035 tUnc SM_State_3_s0
10.314 -0.064 tSu 1 SM_State_3_s0
Path Statistics:
Clock Skew: 0.413
Setup Relationship: 5.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 1.156, 41.610%; route: 1.238, 44.535%; tC2Q: 0.385, 13.855%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 4

Path Summary:
Slack 2.575
Data Arrival Time 7.774
Data Required Time 10.349
From delay_cnt_10_s0
To delay_cnt_1_s0
Launch Clk fx2_ifclk[R]
Latch Clk fx2_ifclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fx2_ifclk
0.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
0.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
0.413 0.413 tNET RR 1 delay_cnt_10_s0/CLK
0.795 0.382 tC2Q RR 5 delay_cnt_10_s0/Q
1.207 0.413 tNET RR 1 n170_s5/I0
1.786 0.579 tINS RR 1 n170_s5/F
2.199 0.413 tNET RR 1 n170_s1/I0
2.778 0.579 tINS RR 4 n170_s1/F
3.190 0.413 tNET RR 1 n164_s2/I0
3.769 0.579 tINS RR 2 n164_s2/F
4.181 0.413 tNET RR 1 n164_s0/I0
4.760 0.579 tINS RR 2 n164_s0/F
5.173 0.413 tNET RR 1 delay_en_s6/I1
5.740 0.567 tINS RR 1 delay_en_s6/F
6.153 0.413 tNET RR 1 delay_en_s5/I3
6.441 0.289 tINS RR 32 delay_en_s5/F
6.854 0.413 tNET RR 1 n128_s1/I2
7.361 0.507 tINS RR 1 n128_s1/F
7.774 0.413 tNET RR 1 delay_cnt_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 fx2_ifclk
10.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
10.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
10.413 0.413 tNET RR 1 delay_cnt_1_s0/CLK
10.349 -0.064 tSu 1 delay_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.679, 49.975%; route: 3.300, 44.829%; tC2Q: 0.382, 5.196%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 2.575
Data Arrival Time 7.774
Data Required Time 10.349
From delay_cnt_10_s0
To delay_cnt_4_s0
Launch Clk fx2_ifclk[R]
Latch Clk fx2_ifclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fx2_ifclk
0.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
0.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
0.413 0.413 tNET RR 1 delay_cnt_10_s0/CLK
0.795 0.382 tC2Q RR 5 delay_cnt_10_s0/Q
1.207 0.413 tNET RR 1 n170_s5/I0
1.786 0.579 tINS RR 1 n170_s5/F
2.199 0.413 tNET RR 1 n170_s1/I0
2.778 0.579 tINS RR 4 n170_s1/F
3.190 0.413 tNET RR 1 n164_s2/I0
3.769 0.579 tINS RR 2 n164_s2/F
4.181 0.413 tNET RR 1 n164_s0/I0
4.760 0.579 tINS RR 2 n164_s0/F
5.173 0.413 tNET RR 1 delay_en_s6/I1
5.740 0.567 tINS RR 1 delay_en_s6/F
6.153 0.413 tNET RR 1 delay_en_s5/I3
6.441 0.289 tINS RR 32 delay_en_s5/F
6.854 0.413 tNET RR 1 n125_s1/I2
7.361 0.507 tINS RR 1 n125_s1/F
7.774 0.413 tNET RR 1 delay_cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 fx2_ifclk
10.000 0.000 tCL RR 1 fx2_ifclk_ibuf/I
10.000 0.000 tINS RR 684 fx2_ifclk_ibuf/O
10.413 0.413 tNET RR 1 delay_cnt_4_s0/CLK
10.349 -0.064 tSu 1 delay_cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.679, 49.975%; route: 3.300, 44.829%; tC2Q: 0.382, 5.196%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%